Particular embodiments generally relate to resistor capacitor (RC) oscillators.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Generation of a high-accuracy clock signal is important for the operation of both digital blocks and many analog circuits, such as charge pumps, buck regulators, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and chopper amplifiers. One way to generate a high-accuracy clock signal is to use a phase lock loop (PLL) with a crystal oscillator to provide the reference frequency. The problem is that this solution is very expensive in cost because it requires an external crystal for the crystal oscillator. In terms of chip area and power, this solution is also expensive because of the implementation of the PLL. As a consequence, the solution is used only in cases where a very high accuracy and low jitter clock is required, such as in high resolution ADCs and DACs.
In other applications, an RC oscillator is used. In one example, an RC oscillator is a relaxation oscillator. A relaxation oscillator is an RC oscillator that is based upon the behavior of the oscillator's return to equilibrium after being perturbed. FIG. 1 shows an example of a conventional relaxation oscillator 100. When a switch 102 is in a high position as shown in FIG. 1, a capacitor 104 is charged with a constant current I0. As soon as a voltage, Vc, across capacitor 104 reaches a threshold voltage VH, the output of a comparator 106a goes high. In a set reset (SR) latch 108, the SR latch is set and the position of switch 102 is reversed to the low position.
As a consequence, capacitor 104 is discharged with the current I0 and when the voltage across capacitor 104 reaches a threshold voltage VL, the output of comparator 106b goes high. The SR latch 108 is reset and the position of switch 102 is reversed again to the high position. This causes an output clock frequency (CLK) from SR latch 108 of:
  f  =                    I        0                    2        ⁢                                  ⁢                  C          ⁡                      (                                          V                H                            -                              V                L                                      )                                .  
FIG. 2 shows waveforms for conventional oscillator 1-100. A graph 200 shows a waveform 201 of the voltage, VC, across capacitor 104 over time. A graph 202 shows a clock signal (CLK) 203 that is generated. At a point 204, the voltage across capacitor 104 reaches VH. At this point, the clock signal should go high. However, due to a delay of comparator 106a, at a point 206, comparator 106a goes high and then the clock signal goes low. A delay of td from an ideal clock frequency results.
At a point 208, the voltage across capacitor 104 has hit the lower threshold voltage VL. There may be time variation td due to a delay of comparator 106b that may cause comparator 106b to go low with a certain amount of delay. This causes the output clock frequency go low with a delay td also. This results in a lower frequency compared to an ideal frequency of a clock signal shown in dotted lines.
FIG. 3 shows another example of a conventional relaxation oscillator 1-100. In this example, a single comparator 1-106 is used. In this case, when switch 1-102 is open, capacitor 1-104 is charged. When the voltage, Vc, across capacitor 1-104 reaches Vthr, then the output of comparator 1-106 goes high. Switch 1-102 is then closed and capacitor 1-104 is discharged. When capacitor 1-104 is discharged, the output of comparator 1-106 goes low, and switch 1-102 is open. Comparator 1-106 outputs a series of impulses. A D flip flop 108 receives the impulses and outputs a 50% duty cycle clock signal (CLK) with the output frequency of:
  f  =            I      0              2      ⁢                          ⁢              C        ⁡                  (                      V            thr                    )                    
FIG. 4 shows an example of waveforms of oscillator 1-100 of FIG. 3. In a graph 400, a waveform 408 for the voltage (VC) across capacitor 1-104 is shown. In a graph 402, a waveform 410 the output of comparator 1-106 is shown. A clock signal (CLK) 412 is shown in graph 404. When the voltage across capacitor 1-104 reaches Vthr, the output of comparator 1-106 should go high. When the switch is closed and capacitor 1-104 is quickly discharged, the output of comparator 1-106 goes low. Thus, a sequence of impulses is provided in graph 402 where a 50% duty cycle clock signal is output.
Because of the delay of comparator 1-106, the frequency of the clock signal is lower than the ideal frequency. For example, a delay td shown at 414 causes comparator 1-106 to go high with a delay, which causes a delay td in the clock frequency going low. This results in a lower frequency compared to an ideal frequency of a clock signal shown in dotted lines.
Accordingly, one of the problems with oscillators 1-100 is that the delay of comparator(s) 106 affects the clock frequency. This delay varies with the process, temperature and supply voltage. The clock frequency is dependent on the threshold voltage of the comparator(s). The equations for the frequency above include the value of the threshold voltages for comparator(s) 106. Thus, as the threshold voltages exhibit a process, temperature, and supply voltage sensitivity, the output clock frequency also varies. The sensitivity may be reduced by designing a fast comparator to reduce the delay but the power consumption increases a lot in this case, especially with the use of high frequency clocks.
Another problem of relaxation oscillator 1-100 is that it requires a constant current I0, but the constant current varies with process, temperature, and supply voltage variations. In order to generate a constant current independent of process, temperature, and supply voltage variations, it is necessary to have a bandgap and an external resistor, Rext. A bandgap is a circuit that generates a precise voltage. The external resistor is external to a chip including oscillator 1-100. The external resistor is needed because integrated resistors may have large variations with process and temperature. The current generated is I0=VBG/Rext, where VBG is the voltage generated by the bandgap. The bandgap is also required to generate precise thresholds VH and VL, or Vthr. Thus, to implement relaxation oscillator 1-100, a fast comparator, a bandgap, and an external resistor are required. which increases cost and complexity.
Other solutions exist in which the output clock frequency is independent of the delay of comparators 106 of FIGS. 1 and 3. However, this requires increased circuit complexity, which raises cost. Further, an op-amp always needs to be used as a comparator 1-106 because threshold voltages are compared with the voltage across capacitor 1-104. Consequently, relaxation oscillators 1-100 are expensive in terms of power because they require at least a high gain op-amp and a bandgap, and in terms of cost, because they require an external resistor.